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1/35 not for new design may 1999 this is information on a product still in production but not recommended for new designs. m36w108t m36w108b 8 mbit (1mb x8, boot block) flash memory and 1 mbit (128kb x8) sram low voltage multi-memory product n m36w108t and m36w108b are replaced respectively by the m36w108at and m36w108ab n supply voltage Cv ccf = v ccs = 2.7v to 3.6v: for program, erase and read n access time: 100ns n low power consumption C read: 40ma max. (sram chip) C stand-by: 30a max. (sram chip) C read: 10ma max. (flash chip) C stand-by: 100a max. (flash chip) flash memory n 8 mbit (1mb x 8) boot block erase n programming time: 10s typical n program/erase controller (p/e.c.) C program byte-by-byte C status register bits and ready/busy output n memory blocks C boot block (top or bottom location) C parameter and main blocks n block, multi-block and chip erase n erase suspend and resume modes C read and program another block during erase suspend n 100,000 program/erase cycles per block n electronic signature C manufacturer code: 20h C device code, m36w108t: d2h C device code, m36w108b: dch sram n 1 mbit (128kb x 8) n power down features using two chip enable inputs n low v cc data retention: 2v bga lga lbga48 (zm) 6 x 8 solder balls lga48 (zn) 6 x 8 solder lands figure 1. logic diagram ai02509 20 a0-a19 w dq0-dq7 v ccf m36w108t m36w108b ef v ss 8 g rp rb v ccs e1s e2s
m36w108t, m36w108b 2/35 description the m36w108 is multi-chip device containing an 8 mbit boot block flash memory and a 1 mbit of sram. the device is offered in the new chip scale package solutions: lbga48 1.0 mm ball pitch and lga48 1.0 mm land pitch. the two components, of the package's overall 9 mbit of memory, are distinguishable by use of the three chip enable lines: ef for the flash memory, e1s and e2s for the sram. the flash memory component is identical with the m29w008 device. it is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a byte-by-byte ba- sis using only a single 2.7v to 3.6v v ccf supply. for program and erase operations the necessary high voltages are generated internally. the device can also be programmed in standard program- mers. the array matrix organization allows each block to be erased and reprogrammed without af- fecting other blocks. instructions for read/reset, auto select for read- ing the electronic signature, programming, block figure 2. lbga and lga connections (top view) c b a 6 5 4 3 2 1 e d f g a11 a14 a1 nc ef v ss a2 a3 dq3 nc nc a4 a7 v ccf nc a0 v ss a8 a18 v ccs dq1 dq2 dq4 a5 nc w dq7 dq5 a19 nc a6 dq0 a10 e1s ai02508 g h e2s rb a13 dq6 nc a9 a15 a12 nc a16 nc rp a17 table 1. signal names a0-a16 address inputs a17-a19 address inputs for flash chip dq0-dq7 data input/outputs, command inputs for flash chip ef chip enable for flash chip e1s , e2s chip enable for sram chip g output enable w write enable rp reset for flash chip rb ready/busy output for flash chip v ccf supply voltage for flash chip v ccs supply voltage for sram chip v ss ground
3/35 m36w108t, m36w108b and chip erase, erase suspend and resume are written to the device in cycles of commands to a command interface using standard microproces- sor write timings. the sram component is a low power sram that features fully static operation requiring no external clocks or timing strobes, with equal address ac- cess and cycle times. it requires a single 2.7v to 3.6v v ccs supply, and all inputs and outputs are ttl compatible. signal descriptions see figure 1 and table 1. address inputs (a0-a16). addresses a0 to a16 are common inputs for the flash chip and the sram chip. the address inputs for the flash memory or the sram array are latched during a write operation on the falling edge of flash chip enable (ef ), sram chip enable (e1s or e2s) or write enable (w ). address inputs (a17-a19). address a17 to a19 are address inputs for the flash chip. they are latched during a write operation on the falling edge of flash chip enable (ef ) or write enable (w ). data input/outputs (dq0-dq7). the input is data to be programmed in the flash or sram memory array or a command to be written to the c.i. of the flash chip. both are latched on the ris- ing edge of flash chip enable (ef ), sram chip enable (e1s or e2s) or write enable (w ). the output is data from the flash memory or sram ar- ray, the electronic signature manufacturer or de- vice codes or the status register data polling bit dq7, the toggle bits dq6 and dq2, the error bit dq5 or the erase timer bit dq3. outputs are valid when flash chip enable (ef ) or sram chip en- able (e1s or e2s) and output enable (g ) are ac- tive. the output is high impedance when the both the flash chip and the sram chip are deselected or the outputs are disabled and when reset (rp ) is at a v il . flash chip enable (ef ). the chip enable input for flash activates the memory control logic, input buffers, decoders and sense amplifiers. ef at v ih deselects the memory and reduces the power con- sumption to the standby level. ef can also be used to control writing to the command register and to the flash memory array, while w remains at v il . it is not allowed to set ef at v il , e1s at v il and e2s at v ih at the same time. sram chip enable (e1s , e2s). the chip en- able inputs for sram activate the memory control logic, input buffers, decoders and sense amplifi- ers. e1s at v ih or e2s at v il deselects the mem- ory and reduces the power consumption to the standby level. e1s and e2s can also be used to control writing to the sram memory array, while w remains at v il . it is not allowed to set ef at v il , e1s at v il and e2s at v ih at the same time. output enable (g ). the output enable gates the outputs through the data buffers during a read op- eration. when g is high the outputs are high im- pedance. write enable (w ). the write enable input con- trols writing to the command register of the flash chip and address/data latches. table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition s above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum voltage may undershoot to C2v during transition and for less than 20ns. 3. depends on range. symbol parameter value unit t a ambient operating temperature (3) C40 to 85 c t bias temperature under bias C50 to 125 c t stg storage temperature C65 to 150 c v io (2) input or output voltage C0.5 to v cc +0.5 v v ccf flash chip supply voltage C0.6 to 5 v v ccs sram chip supply voltage C0.3 to 4.6 v v (ef , rp ) ef , rp voltage 0.6 to 13.5 v pd power dissipation 0.7 w
m36w108t, m36w108b 4/35 reset input (rp ). the reset input provides hardware reset of the flash chip. reset of the flash memory is achieved by pulling rp to v il for at least t plpx . when the reset pulse is given, if the flash memory is in read or standby modes, it will be available for new operations in t phel after the rising edge of rp . if the flash memory is in erase or program mode the reset will take t plyh during which the ready/ busy (rb ) signal will be held at v il . the end of the flash memory reset will be indicated by the rising edge of rb . a hardware reset during an erase or program operation will corrupt the data being pro- grammed or the block(s) being erased. see table 17 and figure 9. ready/busy output (rb ). ready/busy is an open-drain output of the flash chip. it gives the in- ternal state of the program/erase controller (p/ e.c.) of the flash device. when rb is low, the flash device is busy with a program or erase op- eration and it will not accept any additional pro- gram or erase instructions except the erase suspend instruction. when rb is high, the flash device is ready for any read, program or erase operation. the rb will also be high when the flash memory is put in erase suspend or standby modes. v ccf supply voltage. flash memory power sup- ply for all operations (read, program and erase). v ccs supply voltage. sram power supply for all operations (read, program). v ss ground. v ss is the reference for all voltage measurements. power supply power up. the flash memory command inter- face is reset on power up to read array. either flash chip enable (ef ) or write enable (w ) inputs must be tied to v ih during power up to allow max- imum security and the possibility to write a com- mand on the first rising edge of ef and w . any write cycle initiation is blocked when v ccf is below v lko . supply rails. normal precautions must be taken for supply voltage decoupling; each device in a system should have the v ccf , v ccs rails decou- pled with a 0.1f capacitor close to the v ccf , v ccs and v ss pins. the pcb trace widths should be sufficient to carry the v ccf and v ccs program currents and the v ccf erase current required. table 3. main operation modes (1) note: 1. x = v il or v ih . operation mode ef e1s e2s g w rp dq0-dq7 flash chip read v il v ih x v il v ih v ih data output v il x v il v il v ih v ih data output sram chip read v ih v il v ih v il v ih x data output flash chip write v il v ih x v ih v il v ih data input v il x v il v ih v il v ih data input sram chip write v ih v il v ih x v il x data input flash chip output disable x v ih x v ih v ih xhi-z xx v il v ih v ih xhi-z sram chip output disable v ih v il v ih v ih v ih xhi-z flash chip stand-by v ih xx xx v ih hi-z flash chip reset x v ih xxx v il hi-z xx v il xx v il hi-z sram chip stand-by x v ih xxx v il hi-z xx v il xx v il hi-z
5/35 m36w108t, m36w108b figure 3. internal functional arrangement ai02444 v ccs 8 mbit flash memory (1mb x 8) rp rb ef w g 1 mbit sram (128 kb x 8) a0-a16 e1s e2s v ss v ccf v ss a0-a19 dq0-dq7
m36w108t, m36w108b 6/35 flash memory component organization and architecture organization. the flash chip is organized as 1mbit x 8. the memory uses the address inputs a0-a19 and the data input/outputs dq0-dq7. memory control is provided by chip enable (ef ), output enable (g ) and write enable (w ) inputs. erase and program operations are controlled by an internal program/erase controller (p/e.c.). status register data output on dq7 provides a data polling signal, while status register data out- puts on dq6 and dq2 provide toggle signals to indicate the state of the p/e.c. operations. a ready/busy (rb ) output indicates the completion of the internal algorithms. memory blocks. the device features asymmetri- cally blocked architecture providing system mem- ory integration. both top and bottom boot block devices have an array of 19 blocks, one boot block of 16k bytes, two parameter blocks of 8k bytes, one main block of 32k bytes and fifteen main blocks of 64k bytes. the top boot block version has the boot block at the top of the mem- ory address space and the bottom boot block ver- sion locates the boot block starting at the bottom. the memory maps and block address tables are showed in figures 4, 5 and tables 4, 5. each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. the erase opera- tions are managed automatically by the p/e.c. the block erase operation can be suspended in order to read from or program to any block not be- ing erased, and then resumed. device operations the following operations can be performed using the appropriate bus cycles: read array, write command, output disable, standby and reset (see table 6). read. read operations are used to output the contents of the memory array, the electronic sig- nature or the status register. both chip enable (ef ) and output enable (g ) must be low, with write enable (w ) high, in order to read the output of the memory. table 4. top boot block, flash block address size (kword) address range 16 fc000h-fffffh 8 fa000h-fbfffh 8 f8000h-f9fffh 32 f0000h-f7fffh 64 e0000h-effffh 64 d0000h-dffffh 64 c0000h-cffffh 64 b0000h-bffffh 64 a0000h-affffh 64 90000h-9ffffh 64 80000h-8ffffh 64 70000h-7ffffh 64 60000h-6ffffh 64 50000h-5ffffh 64 40000h-4ffffh 64 30000h-3ffffh 64 20000h-2ffffh 64 10000h-1ffffh 64 00000h-0ffffh table 5. bottom boot block, flash block address size (kword) address range 64 f0000h-fffffh 64 e0000h-effffh 64 d0000h-dffffh 64 c0000h-cffffh 64 b0000h-bffffh 64 a0000h-affffh 64 90000h-9ffffh 64 80000h-8ffffh 64 70000h-7ffffh 64 60000h-6ffffh 64 50000h-5ffffh 64 40000h-4ffffh 64 30000h-3ffffh 64 20000h-2ffffh 64 10000h-1ffffh 32 08000h-0ffffh 8 06000h-07fffh 8 04000h-05fffh 16 00000h-03fffh
7/35 m36w108t, m36w108b write. write operations are used to give instruc- tion commands to the memory or to latch input data to be programmed. a write operation is initi- ated when chip enable (ef ) is low and write en- able (w ) is at v il with output enable (g ) at v ih . addresses are latched on the falling edge of w or ef whichever occurs last. commands and input data are latched on the rising edge of w or ef whichever occurs first. output disable. the data outputs are high im- pedance when the output enable (g ) is at v ih with write enable (w ) at v ih . standby. the memory is in standby when chip enable (ef ) is at v ih and the p/e.c. is idle. the power consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable (g ) or write enable (w ) in- puts. automatic standby. after 150ns of bus inactivity and when cmos levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the cmos standby value, while outputs still drive the bus. instructions and commands seven instructions are defined (see table 7) to perform read array, auto select (to read the elec- tronic signature), program, block erase, chip erase, erase suspend and erase resume. the internal p/e.c. automatically handles all timing and verification of the program and erase opera- tions. the status register data polling, toggle, error bits and the rb output may be read at any time, during programming or erase, to monitor the progress of the operation. instructions, made up of commands written in cy- cles, can be given to the program/erase controller through a command interface (c.i.). the c.i. latches commands written to the memory. commands are made of address and data se- quences. two coded cycles unlock the command interface. they are followed by an input command or a confirmation command. the coded sequence consists of writing the data aah at the address 5555h during the first cycle and the data 55h at the address 2aaah during the second cycle. table 6. flash user bus operations (1) note: 1. x = v il or v ih . table 7. read flash electronic signature operation ef g w rp a0 a1 a6 a9 a12 a15 dq0-dq7 read byte v il v il v ih v ih a0 a1 a6 a9 a12 a15 data output write byte v il v ih v il v ih a0 a1 a6 a9 a12 a15 data input output disable v il v ih v ih v ih xxxxxx hi-z stand-by v ih xx v ih xxxxxx hi-z reset x x x v il xxxxxx hi-z code device ef g w a0 a1 other addresses dq0-dq7 manufact. code v il v il v ih v il v il dont care 20h device code m36w108t v il v il v ih v ih v il dont care d2h m36w108b v il v il v ih v ih v il dont care dch
m36w108t, m36w108b 8/35 instructions are composed of up to six cycles. the first two cycles input a coded sequence to the command interface which is common to all in- structions (see table 9). the third cycle inputs the instruction set-up command. subsequent cycles output the addressed data or electronic signature for read operations. in order to give additional data protection, the instructions for program and block or chip erase require further command in- puts. for a program instruction, the fourth com- mand cycle inputs the address and data to be programmed. for an erase instruction (block or chip), the fourth and fifth cycles input a further coded sequence before the erase confirm com- mand on the sixth cycle. erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. when power is first applied or if v ccf falls below v lko , the command interface is reset to read ar- ray. command sequencing must be followed exactly. any invalid combination of commands will reset the device to read array. the increased number of cycles has been chosen to assure maximum data security. read/reset (rd) instruction. the read/reset instruction consists of one write cycle giving the command f0h. it can be optionally preceded by the two coded cycles. subsequent read opera- tions will read the memory array addressed and output the data read. a wait state of t plyh is nec- essary after read/reset prior to any valid read if the memory was in an erase or program mode when the rd instruction is given (see table 17 and figure 9). auto select (as) instruction. this instruction uses the two coded cycles followed by one write cycle giving the command 90h to address 5555h for command set-up. a subsequent read will out- put the manufacturer code or the device code (electronic signature) depending on the levels of a0 and a1 (see table 7). the electronic signature can be read from the memory allowing program- ming equipment or applications to automatically match their interface to the characteristics of the flash memory. the manufacturer code, 20h, is output when the addresses lines a0 and a1 are at v il , the device code is output when a0 is at v ih with a1 at v il . other address inputs are ignored. program (pg) instruction. this instruction uses four write cycles. the program command a0h is written to address 5555h on the third cycle after two coded cycles. a fourth write operation latch- es the address and the data to be written and starts the p/e.c. read operations output the sta- tus register bits after the programming has start- ed. memory programming is made only by writing '0' in place of '1'. status bits dq6 and dq7 deter- mine if programming is on-going and dq5 allows verification of any possible error. programming at an address not in blocks being erased is also pos- sible during erase suspend. in this case, dq2 will toggle at the address being programmed. table 8. flash commands hex code command 00h invalid/reserved 10h chip erase confirm 20h reserved 30h block erase resume/confirm 80h set-up erase 90h read electronic signature/ block protection status a0h program b0h erase suspend f0h read array/reset
9/35 m36w108t, m36w108b block erase (be) instruction. this instruction uses a minimum of six write cycles. the erase set-up command 80h is written to address 5555h on third cycle after the two coded cycles. the block erase confirm command 30h is similarly written on the sixth cycle after another two coded cycles. during the input of the second command an address within the block to be erased is given and latched into the memory. additional block erase confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further cod- ed cycles. the erase will start after the erase tim- eout period (see erase timer bit dq3 description). thus, additional erase confirm commands for oth- er blocks must be given within this delay. the input of a new erase confirm command will restart the timeout period. the status of the internal timer can be monitored through the level of dq3, if dq3 is '0' the block erase command has been given and the timeout is running, if dq3 is '1', the timeout has expired and the p/e.c. is erasing the block(s). if the second command given is not an erase con- firm or if the coded cycles are wrong, the instruc- tion aborts, and the device is reset to read array. it is not necessary to program the block with 00h as the p/e.c. will do this automatically before to erasing to ffh. read operations after the sixth ris- ing edge of w or ef output the status register bits. during the execution of the erase by the p/e.c., the memory only accepts the erase suspend (es) and read/reset (rd) instructions. a read/reset command will definitively abort erasure and result in invalid data in blocks being erased. a complete state of the block erase operation is given by the status register bits (see dq2, dq3, dq5, dq6 and dq7 description). chip erase (ce) instruction. this instruction uses six write cycles. the erase set-up command 80h is written to address 5555h on the third cycle after the two coded cycles. the chip erase con- firm command 10h is similarly written on the sixth cycle after another two coded cycles. if the sec- ond command given is not an erase confirm or if the coded sequence is wrong, the instruction aborts and the device is reset to read array. it is not necessary to program the array with 00h first as the p/e.c. will automatically do this before erasing it to ffh. read operations after the sixth rising edge of w or ef output the status register bits. a complete state of the chip erase operation is given by the status register bits (see dq2, dq3, dq5, dq6 and dq7 description). erase suspend (es) instruction. the block erase operation may be suspended by this in- struction which consists of writing the command b0h without any specific address. no coded cy- cles are required. it permits reading of data from another block and programming in another block while an erase operation is in progress. erase sus- pend is accepted only during the block erase in- struction execution. writing this command during the erase timeout period will, in addition to sus- pending the erase, terminate the timeout. the toggle bit dq6 stops toggling when the p/e.c. is suspended. the toggle bits will stop toggling be- tween 0.1s and 15s after the erase suspend (es) command has been written. the device will then automatically be set to read memory array mode. when erase is suspended, a read from blocks being erased will output dq2 toggling and dq6 at '1'. a read from a block not being erased returns valid data. during suspension the memory will respond only to the erase resume (er) and the program (pg) instructions. a program opera- tion can be initiated during erase suspend in one of the blocks not being erased. it will result in both dq2 and dq6 toggling when the data is being pro- grammed. a read/reset command will definitively abort erasure and result in invalid data in the blocks being erased. erase resume (er) instruction. if an erase suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any coded cycles.
m36w108t, m36w108b 10/35 table 9. flash instructions (1) note: 1. commands not interpreted in this table will default to read array mode. 2. a wait of t plyh is necessary after a read/reset command if the memory was in an erase, erase suspend or program mode before starting any new operation (see table 14 and figure 7). 3. x = dont care. 4. the first cycles of the rd or as instructions are followed by read operations. any number of read cycles can occur after the com- mand cycles. 5. signature address bits a0, a1, at v il will output manufacturer code (20h). address bits a0 at v ih and a1, at v il will output device code. 6. block protection address: a0, at v il , a1 at v ih and a13-a19 within the block will output the block protection status. 7. for coded cycles address inputs a15-a19 are dont care. 8. optional, additional blocks addresses must be entered within the erase timeout delay after last write entry, timeout status c an be verified through dq3 value (see erase timer bit dq3 description). when full command is entered, real data polling or toggle bit until erase is completed or suspended. 9. read data polling, toggle bits or rb until erase completes. 10. during erase suspend, read and data program functions are allowed in blocks not being erased. mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. 7th cyc. rd (2,4) read/reset memory array 1+ addr. (3,7) x read memory array until a new write cycle is initiated. data f0h 3+ addr. (3,7) 5555h 2aaah 5555h read memory array until a new write cycle is initiated. data aah 55h f0h as (4) auto select 3+ addr. (3,7) 5555h 2aaah 5555h read electronic signature or block protection status until a new write cycle is initiated. see note 5 and 6. data aah 55h 90h pg program 4 addr. (3,7) 5555h 2aaah 5555h program address read data polling or toggle bit until program completes. data aah 55h a0h program data be block erase 6 addr. (3,7) 5555h 2aaah 5555h 5555h 2aaah block address additional block (8) data aah 55h 80h aah 55h 30h 30h ce chip erase 6 addr. (3,7) 5555h 2aaah 5555h 5555h 2aaah 5555h note 9 data aah 55h 80h aah 55h 10h es (10) erase suspend 1 addr. (3,7) x read until toggle stops, then read all the data needed from any block(s) not being erased then resume erase. data b0h er erase resume 1 addr. (3,7) x read data polling or toggle bits until erase completes or erase is suspended another time. data 30h
11/35 m36w108t, m36w108b table 10. flash status register bits (1) note: 1. logic level 1 is high, 0 is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. dq name logic level definition note 7 data polling 1 erase complete or erase block in erase suspend indicates the p/e.c. status, check during program or erase, and on completion before checking bits dq5 for program or erase success. 0 erase on-going dq program complete or data of non erase block during erase suspend dq program on-going 6 toggle bit -1-0-1-0-1-0-1- erase or program on-going successive reads output complementary data on dq6 while programming or erase operations are on-going. dq6 remains at constant level when p/e.c. operations are completed or erase suspend is acknowledged. dq program complete -1-1-1-1-1-1-1- erase complete or erase suspend on currently addressed block 5 error bit 1 program or erase error this bit is set to 1 in the case of programming or erase failure. 0 program or erase on-going 4 reserved 3 erase time bit 1 erase timeout period expired p/e.c. erase operation has started. only possible command entry is erase suspend (es). 0 erase timeout period on-going an additional block to be erased in parallel can be entered to the p/e.c. 2 toggle bit -1-0-1-0-1-0-1- chip erase, erase or erase suspend on the currently addressed block. erase error due to the currently addressed block (when dq5 = 1) indicates the erase status and allows to identify the erased block. 1 program on-going, erase on-going on another block or erase complete dq erase suspend read on non erase suspend block 1 reserved 0 reserved
m36w108t, m36w108b 12/35 status register bits p/e.c. status is indicated during execution by data polling on dq7, detection of toggle on dq6 and dq2, or error on dq5 and erase timer dq3 bits. any read attempt during program or erase com- mand execution will automatically output these five status register bits. the p/e.c. automatically sets bits dq2, dq3, dq5, dq6 and dq7. other bits (dq0, dq1 and dq4) are reserved for future use and should be masked (see table 10 and ta- ble 11). data polling bit (dq7). when programming op- erations are in progress, this bit outputs the com- plement of the bit being programmed on dq7. during erase operation, it outputs a '0'. after com- pletion of the operation, dq7 will output the bit last programmed or a '1' after erasing. data polling is valid and only effective during p/e.c. operation, that is after the fourth w pulse for programming or after the sixth w pulse for erase. it must be per- formed at the address being programmed or at an address within the block being erased. if all the blocks selected for erasure are protected, dq7 will be set to '0' for about 100s, and then return to the previous addressed memory data value. see fig- ure 9 for the data polling flowchart and figure 11 for the data polling waveforms. dq7 will also flag the erase suspend mode by switching from '0' to '1' at the start of the erase suspend. in order to monitor dq7 in the erase suspend mode an ad- dress within a block being erased must be provid- ed. for a read operation in erase suspend mode, dq7 will output '1' if the read is attempted on a block being erased and the data value on oth- er blocks. during program operation in erase sus- pend mode, dq7 will have the same behaviour as in the normal program execution outside of the suspend mode. toggle bit (dq6). when programming or eras- ing operations are in progress, successive at- tempts to read dq6 will output complementary data. dq6 will toggle following toggling of either g , or ef when g is at v il . the operation is complet- ed when two successive reads yield the same out- put data. the next read will output the bit last programmed or a '1' after erasing. the toggle bit dq6 is valid only during p/e.c. operations, that is after the fourth w pulse for programming or after the sixth w pulse for erase. if the blocks selected for erasure are protected, dq6 will toggle for about 100s and then return back to read. dq6 will be set to '1' if a read operation is attempted on an erase suspend block. when erase is suspended dq6 will toggle during programming operations in a block different to the block in erase suspend. ei- ther ef or g toggling will cause dq6 to toggle. see figure 11 for toggle bit flowchart and figure 15 for toggle bit waveforms. toggle bit (dq2). this toggle bit, together with dq6, can be used to determine the device status during the erase operations. it can also be used to identify the block being erased. during erase or erase suspend a read from a block being erased will cause dq2 to toggle. a read from a block not being erased will set dq2 to '1' during erase and to dq2 during erase suspend. during chip erase a read operation will cause dq2 to toggle as all blocks are being erased. dq2 will be set to '1' dur- ing program operation and when erase is com- plete. after erase completion and if the error bit dq5 is set to '1', dq2 will toggle if the faulty block is addressed. error bit (dq5). this bit is set to '1' by the p/e.c. when there is a failure of programming, block erase, or chip erase that results in invalid data in the memory block. in case of an error in block erase or program, the block in which the error oc- curred or to which the programmed data belongs, must be discarded. the dq5 failure condition will also appear if a user tries to program a '1' to a lo- cation that is previously programmed to '0'. other blocks may still be used. the error bit resets after a read/reset (rd) instruction. in case of success of program or erase, the error bit will be set to '0'. erase timer bit (dq3). this bit is set to '0' by the p/e.c. when the last block erase command has been entered to the command interface and it is awaiting the erase start. when the erase timeout period is finished, after 50s to 90s, dq3 returns to '1'. table 11. flash polling and toggle bits (1) note: 1. toggle if the address is within a block being erased. 1 if the address is within a block not being erased. mode dq7 dq6 dq2 program dq7 toggle 1 erase 0 toggle note 1 erase suspend read (in erase suspend block) 1 1 toggle erase suspend read (outside erase suspend block) dq7 dq6 dq2 erase suspend program dq7 toggle n/a
13/35 m36w108t, m36w108b table 12. flash program/erase times and endurance (t a = 0 to 70 c; v cc = 2.7 v to 3.6 v) parameter flash memory chip unit min typ typical after 100k w/e cycles max chip erase (preprogrammed) 5 3.3 sec chip erase 12 sec boot block erase 2.4 sec parameter block erase 2.3 sec main block (32kb) erase 2.7 sec main block (64kb) erase 3.3 15 sec chip program (byte) 8 8 sec byte program 10 10 s program/erase cycles (per block) 100,000 cycles
m36w108t, m36w108b 14/35 sram component device operations the following operations can be performed using the appropriate bus cycles: read array, write ar- ray, output disable, power down (see table 13). read. read operations are used to output the contents of the sram array. the sram is in read mode whenever write enable (w ) is at v ih with output enable (g ) at v il , and both chip enables (e1s and e2s) are asserted. valid data will be available at the eight output pins within t avqv after the last stable address, provid- ing g is low, e1s is low and e2s is high. if chip enable or output enable access times are not met, data access will be measured from the limit- ing parameter (t e1lqv , t e2hqv , or t glqv ) rather than the address. data out may be indeterminate at t e1lqx , t e2hqx and t glqx , but data lines will al- ways be valid at t avqv (see table 21, figure 14, figure 15). write. write operations are used to write data in the sram. the sram is in write mode whenever the w and e1s pins are at v il , with e2s at v ih . ei- ther the chip enable inputs (e1s and e2s) or the write enable input (w ) must be de-asserted dur- ing address transitions for subsequent write cy- cles. write begins with the concurrence of both chip enables being active with w at v il . a write begins at the latest transition among e1s going to v il , e2s going to v ih and w going to v il . there- fore, address setup time is referenced to write en- able and both chip enables as t avwl , t ave1l and t ave2h respectively, and is determined by the latter occurring edge. the write cycle can be terminated by the rising edge of e1s , the rising edge of w or the falling edge of e2s, whichever occurs first. if the output is enabled (e1s =v il , e2s=v ih and g =v il ), then w will return the outputs to high im- pedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of op- eration. data input must be valid for t dvwh before the rising edge of write enable, or for t dve1h be- fore the rising edge of e1s or for t dve2l before the falling edge of e2s, whichever occurs first, and re- main valid for t whdx , t e1hdx or t e2ldx (see table 22, figures 17, 18, 19). output disable. the data outputs are high im- pedance when the output enable (g ) is at v ih with write enable (w ) at v ih . power-down. the sram chip has a chip enable power-down feature which invokes an automatic standby mode (see table 21, figure 16) whenever either chip enable is de-asserted (e1s=v ih or e2s=v il ). data retention the sram data retention performances as v ccs go down to v dr are described in table 23 and fig- ures 22, 23. in e1s controlled data retention mode, minimum standby current mode is entered when e1s 3 v ccs C 0.2v and e2s 0.2v or e2s 3 v ccs C 0.2v. in e2s controlled data reten- tion mode, minimum standby current mode is en- tered when e2s 0.2v. table 13. sram user bus operations (1) note: 1. x = v il or v ih . operation e1s e2s w g dq0-dq7 power read v il v ih v ih v il data output active write v il v ih v il x data input active output disable v il v ih v ih v ih hi-z active power down v ih x x x hi-z stand-by ttl x v il x x hi-z stand-by ttl/cmos
15/35 m36w108t, m36w108b table 14. dc characteristics (t a = 0 to 70c, C20 to 85c, C40 to 85c; v ccf = v ccs = 2.7v to 3.6v) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit i li input leakage current 0v v in v ccf / v ccs C1 1 a i lo output leakage current 0v v out v ccf / v ccs C1 1 a i ccf1 flash chip supply current (read) ef = v il , g = v ih , f = 6mhz, v v out v ccf 10 ma i ccf2 (1) flash chip supply current (write) program or erase in progress 20 a i ccf3 flash chip supply current (stand-by) ef = v ccf 0.2v 100 a i ccs1 sram chip supply current (read) e1s = v il , e2s = v ih , f= 10mhz 40 ma e1s = v il , e2s = v ih , f= 1mhz 10 ma i ccs2 (1) sram chip supply current (write) 20 ma i ccs3 sram chip supply current (stand-by) 20 a v ilf flash chip input low voltage C0.5 0.8 v v ihf flash chip input high voltage 0.7 v ccf v ccf + 0.3 v v ils sram chip input low voltage C0.3 0.4 v v ihs sram chip input high voltage 2.2 v ccs + 0.3 v v olf flash chip output low voltage i ol = 1.8ma 0.45 v v ohf flash chip output high voltage i oh = C100a v ccf C 0.4 v v ols sram chip output low voltage i ol = 2.1ma 0.4 v v ohs sram chip output high voltage i oh = C1.0ma 2.2 v table 15. capacitance (1) (t a = 25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf figure 5. ac testing load circuit ai01968 0.8v out c l = 30pf or 100pf c l includes jig capacitance 3.3k w 1n914 device under test table 16. ac measurement conditions input rise and fall times 10ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v figure 4. ac testing input/output waveforms ai01417 3v 0v 1.5v
m36w108t, m36w108b 16/35 table 17. flash read ac characteristics (t a = 0 to 70 c, C20 to 85 c or C40 to 85 c; v ccf = 2.7v to 3.6v) note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of ef without increasing t elqv . 3. to be considered only if the reset pulse is given while the memory is in erase, erase suspend or program mode. 4. see flash-sram switching waveforms. symbol alt parameter test condition flash memory chip unit 100 120 c l = 30pf c l = 100pf min max min max t avav t rc address valid to next address valid ef = v il , g = v il 100 120 ns t avqv t acc address valid to output valid ef = v il , g = v il 100 120 ns t elqx (1) t lz chip enable low to output transition g = v il 00ns t elqv (2) t ce chip enable low to output valid g = v il 100 120 ns t glqx (1) t olz output enabled low to output transition ef = v il 00ns t glqv (2) t oe output enable low to output valid ef = v il 40 50 ns t ehqx t oh chip enable high to output transition g = v il 00ns t ehqz (1) t hz chip enable high to output hi-z g = v il 30 30 ns t ghqx t oh output enable high to output transition ef = v il 00ns t ghqz (1) t df output enable high to output hi-z ef = v il 30 30 ns t axqx t oh address transition to output transition ef = v il , g = v il 00ns t plyh (1,3) t rrb t ready rp low to read mode 10 10 s t phel t rh rp high to chip enable low 50 50 ns t plpx t rp rp pulse width 500 500 ns t ccr (4) chip enabled recovery time 0 0 ns
17/35 m36w108t, m36w108b figure 6. flash read mode ac waveforms ai02511b tavav tavqv taxqx telqx tehqx tglqv tglqx tghqx valid a0-a19 ef g dq0-dq7 telqv valid tehqz tghqz note: write enable (w ) = high.
m36w108t, m36w108b 18/35 table 18. flash write ac characteristics, write enable controlled (t a = 0 to 70 c, C20 to 85 c or C40 to 85 c; v ccf = 2.7v to 3.6v) note: 1. sampled only, not 100% tested. 2. this timing is for temporary block unprotection operation. symbol alt parameter flash memory chip unit 100 120 c l = 30pf c l = 100pf min max min max t avav t wc address valid to next address valid 100 120 ns t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 50 50 ns t dvwh t ds input valid to write enable high 50 50 ns t whdx t dh write enable high to input transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whwl t wph write enable high to write enable low 30 30 ns t avwl t as address valid to write enable low 0 0 ns t wlax t ah write enable low to address transition 50 50 ns t ghwl output enable high to write enable low 0 0 ns t vchel t vcs v cc high to chip enable low 50 50 s t whgl t oeh write enable high to output enable low 0 0 ns t phphh (1,2) t vidr rp rise time to v id 500 500 ns t plpx t rp rp pulse width 500 500 ns t whrl (1) t busy program erase valid to rb delay 90 90 ns t phwl (1) t rsp rp high to write enable low 4 4 s
19/35 m36w108t, m36w108b figure 7. flash write ac waveforms, w controlled note: address are latched on the falling edge of w , data is latched on the rising edge of w . ai02512 ef g w a0-a19 dq0-dq7 valid valid v ccf tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl
m36w108t, m36w108b 20/35 table 19. flash write ac characteristics, chip enable controlled (t a = 0 to 70 c, C20 to 85 c or C40 to 85 c; v ccf = 2.7v to 3.6v) note: 1. sampled only, not 100% tested. 2. this timing is for temporary block unprotection operation. symbol alt parameter flash memory chip unit 100 120 c l = 30pf c l = 100pf min max min max t avav t wc address valid to next address valid 100 120 ns t wlel t ws write enable low to chip enable low 0 0 ns t eleh t cp chip enable low to chip enable high 50 50 ns t dveh t ds input valid to chip enable high 50 50 ns t ehdx t dh chip enable high to input transition 0 0 ns t ehwh t wh chip enable high to write enable high 0 0 ns t ehel t cph chip enable high to chip enable low 30 20 ns t avel t as address valid to chip enable low 0 0 ns t elax t ah chip enable low to address transition 50 50 ns t ghel output enable high chip enable low 0 0 ns t vchwl t vcs v cc high to write enable low 50 50 s t ehgl t oeh chip enable high to output enable low 0 0 ns t phphh (1,2) t vidr rp rise time to v id 500 500 ns t plpx t rp rp pulse width 500 500 ns t ehrl (1) t busy program erase valid to rb delay 90 90 ns t phwl (1) t rsp rp high to write enable low 4 4 s
21/35 m36w108t, m36w108b figure 8. flash write ac waveforms, ef controlled note: address are latched on the falling edge of ef , data is latched on the rising edge of ef . ai02513 ef g w a0-a19 dq0-dq7 valid valid v ccf tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl figure 9. flash read and write ac waveforms, rp related ai02514 rb w rp tplpx tphwl tplyh tphphh ef tphel
m36w108t, m36w108b 22/35 table 20. flash data polling and toggle bits ac characteristics (1) (t a = 0 to 70 c, C20 to 85 c or C40 to 85 c; v ccf = 2.7v to 3.6v) note: 1. all other timings are defined in read ac characteristics table. symbol parameter flash memory chip unit 100 120 c l = 30pf c l = 100pf min max min max t whq7v write enable high to dq7 valid (program, w controlled) 10 2400 10 2400 ms write enable high to dq7 valid (chip erase, w controlled) 1.0 60 1.0 60 sec t ehq7v chip enable high to dq7 valid (program, ef controlled) 10 2400 10 2400 s chip enable high to dq7 valid (chip erase, ef controlled) 1.0 60 1.0 60 sec t q7vqv q7 valid to output valid (data polling) 40 50 ns t whqv write enable high to output valid (program) 10 2400 10 2400 s write enable high to output valid (chip erase) 1.0 60 1.0 60 sec t ehqv chip enable high to output valid (program) 10 2400 10 2400 s chip enable high to output valid (chip erase) 1.0 60 1.0 60 sec
23/35 m36w108t, m36w108b figure 10. flash data polling dq7 ac waveforms ai02515b ef g w a0-a19 dq7 ignore valid dq0-dq6 address (within blocks) tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle memory array read cycle data polling read cycles last write cycle of program or erase instruction telqv
m36w108t, m36w108b 24/35 figure 11. flash data toggle dq6, dq2 ac waveforms ai02516 ef g w a0-a19 dq6,dq2 tavqv stop toggle last write cycle of program of erase instruction valid valid valid ignore data toggle read cycle memory array read cycle twhqv tehqv telqv tglqv data toggle read cycle dq0-dq1,dq3-dq5,dq7 note: all other timings are as a normal read cycle.
25/35 m36w108t, m36w108b figure 12. flash data polling flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai01369 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no figure 13. flash data toggle flowchart read dq2, dq5 & dq6 start read dq2, dq6 fail pass ai01873 dq2, dq6 = toggle no no yes yes dq5 = 1 no yes dq2, dq6 = toggle
m36w108t, m36w108b 26/35 table 21. sram read ac characteristics (t a = 0 to 70 c, C20 to 85 c or C40 to 85 c; v ccs = 2.7v to 3.6v) note: 1. sampled only. not 100% tested. 2. see flash-sram switching waveforms. symbol parameter sram chip unit 100 c l = 100pf min max t avav read cycle time 100 ns t av qv address valid to output valid 100 ns t e1lqv chip enable 1 low to output valid 100 ns t e2hqv chip enable 2 high to output valid 100 ns t glqv output enable low to output valid 50 ns t e1lqx chip enable 1 low to output transition 10 ns t e2hqx chip enable 2 high to output transition 10 ns t glqx output enable low to output transition 5 ns t e1hqz chip enable 1 high to output hi-z 0 30 ns t e2lqz chip enable 2 low to output hi-z 0 30 ns t ghqz output enable high to output hi-z 0 30 ns t axqx address transition to output transition 15 ns t pu (1) chip enable 1 low or chip enable 2 high to power up 0 ns t pd (1) chip enable 1 high or chip enable 2 low to power down 100 ns t ccr (2) chip enable recovery time 0 ns figure 14. sram read mode ac waveforms, address controlled note: e1s = low, e2s = high, g = low, w = high. ai02436 tavav tavqv taxqx a0-a16 dq0-dq7 valid data valid data valid
27/35 m36w108t, m36w108b figure 15. sram read ac waveforms, e1s , e2s or g controlled note: write enable (w ) = high. ai02435 tavav tavqv taxqx te1lqv te1lqx te1hqz tglqv tglqx tghqz data valid a0-a16 e1s g dq0-dq7 te2hqv te2hqx valid te2lqz e2s figure 16. sram stand-by ac waveforms ai02517 tpd e2s i cc4 tpu i cc5 50% e1s
m36w108t, m36w108b 28/35 table 22. sram write ac characteristics (t a = 0 to 70 c, C20 to 85 c or C40 to 85 c; v ccs = 2.7v to 3.6v) symbol parameter sram chip unit 100 c l = 100pf min max t avav write cycle time 100 ns t av wl address valid to write enable low 0 ns t avw h address valid to write enable high 80 ns t wlwh write enable pulse width 70 ns t whax write enable high to address transition 0 ns t whdx write enable high to input transition 0 ns t whqx write enable high to output transition 0 ns t wlqz write enable low to output hi-z 0 30 ns t av e1l address valid to chip enable 1 low 0 ns t ave 2h address valid to chip enable 2 high 0 ns t e1hax chip enable 1 high to address transition 0 ns t e2lax chip enable 2 low to address transition 0 ns t dvwh input valid to write enable high 40 ns t dve1h input valid to chip enable 1 high 40 ns t dve2l input valid to chip enable 2 low 40 ns figure 17. sram write ac waveforms, w controlled note: output enable (g ) = low. ai02434 tavav twhax tdvwh input valid a0-a16 e1s w dq0-dq7 valid e2s tavwh tave1l tave2h twlwh tavwl twlqz twhdx twhqx
29/35 m36w108t, m36w108b figure 18. sram write ac waveforms, e1s controlled note: output enable (g ) = high. ai02433 tavav te1hax tdve1h a0-a16 e1s w dq0-dq7 valid e2s tave1l tavwl twhdx input valid figure 19. sram write ac waveforms, e2s controlled note: output enable (g ) = high. ai02432 tavav te2lax tdve2l a0-a16 e1s w dq0-dq7 valid e2s tavwl twhdx input valid tave2h
m36w108t, m36w108b 30/35 table 23. sram low v cc data retention characteristics (1, 2) (t a = 0 to 70 c; v ccs = 2.7 v to 3.6 v) note: 1. all other inputs v ih v cc C 0.2v or v il 0.2v. 2. sampled only. not 100% tested. symbol parameter test condition min max unit i ccdr supply current (data retention) v ccs = 3v, e1s 3 v ccs C 0.2v, e2s 3 v ccs C 0.2v or e2s 0.2v, f = 0 20 a v dr supply voltage (data retention) e1s 3 v ccs C 0.2v,e2s 0.2v, f = 0 23.6v t cdr chip disable to power down e1s 3 v ccs C 0.2v,e2s 0.2v, f = 0 0ns t r operation recovery time 5 ms figure 20. sram low v cc data retention ac waveforms, e1s controlled ai02438 2.7 v e1s tcdr e1s 3 v ccs C 0.2v 2.2 v v dr v ss v ccs tr data retention mode
31/35 m36w108t, m36w108b figure 21. sram low v cc data retention ac waveforms, e2s controlled ai02437 2.7 v e2s tcdr e2s 0.2v v dr v ss v ccs tr data retention mode 0.4 v figure 22. flash-sram switching waveforms ai02510 ef e1s e2s tccr tccr
m36w108t, m36w108b 32/35 table 24. ordering information scheme the m36w108t and m36w108b are replaced respectively by the new version m36w108at and m36w108ab. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m36w108t 100 zm 1 t product family m36 = mmp (flash + sram) operating voltage w = 2.7v to 3.6v sram chip size & organization 1 = 1 mbit (128kb x8) flash chip size & orgnization 08 = 8 mbit (1mb x8), boot block array matrix t = top boot b = bottom boot speed 100 = 100 ns 120 = 120 ns package zm = lbga48: 1mm pitch zn = lga48: 1mm pitch temperature range 1 = 0 to 70 c 5 = C20 to 85 c 6 = C40 to 85 c option t = tape & reel packing
33/35 m36w108t, m36w108b table 25. lbga48 - 6 x 8 balls, 1.0 mm pitch, package mechanical data symb mm inches typ min max typ min max a 1.250 1.150 1.350 0.049 0.045 0.053 a1 0.300 0.250 0.350 0.012 0.010 0.014 a2 0.950 C C 0.037 C C b 0.400 0.350 0.450 0.016 0.014 0.018 ddd 0.150 0.006 d 10.000 9.800 10.200 0.394 0.386 0.402 d1 5.000 C C 0.197 C C e 1.000 C C 0.039 C C e 12.000 11.800 12.200 0.472 0.465 0.480 e1 7.000 C C 0.276 C C sd 0.500 C C 0.020 C C se 0.500 C C 0.020 C C figure 23. lbga48 - 6 x 8 balls, 1.0 mm pitch, package outline drawing is not to scale. e1 e d1 d eb sd se a2 a1 a bga-z01 ddd ball "a1"
m36w108t, m36w108b 34/35 table 26. lga48 - 6 x 8 balls, 1.0 mm pitch, package mechanical data symb mm inches typ min max typ min max a 0.950 0.900 1.000 0.037 0.035 0.039 b 0.450 0.420 0.480 0.018 0.017 0.019 d 10.000 9.800 10.200 0.394 0.386 0.402 d1 5.000 C C 0.197 C C d2 9.200 C C 0.362 C C e 1.000 C C 0.039 C C e 12.000 11.800 12.200 0.472 0.465 0.480 e1 7.000 C C 0.276 C C e2 10.200 C C 0.402 C C sd 0.500 C C 0.020 C C se 0.500 C C 0.020 C C figure 24. lga48 - 6 x 8 balls, 1.0 mm pitch, package outline drawing is not to scale. e1 e2 d1 d2 eb sd se a lga-z02 land "a1" e d
35/35 m36w108t, m36w108b information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 1999 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com

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